1. Field of the Invention
The present invention is directed to a programmable, configurable bus system of lines to interconnect electrical components for an electrical/electronics system.
2. Art Background
Megacells are described as block components such as static random access memory (SRAM), microcontrollers, microprocessors and buffers. Sometimes it is desirable to interconnect a plurality of megacells together to provide a larger functional entity. One way to interconnect multiple megacells and logic circuits is through a hardwired bus system. Examples are illustrated in FIGS. 1a, 1b and 1c. illustrates a bus interface to a dual port SRAM megacell. Bus lines include DATA 0-DATA15, READA 0-READA9, WRITEA0-WRITEA9. To couple multiple megacells, the data lines are shared among the coupled cells. However, separate read and write lines would be required for each megacell. To the contrary, if the megacells were coupled to generate a deeper combined megaceu, the data lines would be separate for each megacell and the read and write lines would be shared among the megacells. Control signals are then be used to select a particular megacell for a particular operation. This is illustrated in FIGS. 1b and 1c. 
Such configurations are hardwired and cannot easily be changed to accommodate different configurations. Furthermore, if errors occur in the mask generated, repairs are not easily made, as configurability is minimal. In addition to providing a bus system to interconnect multiple megacells, tristatable input ports are sometimes used to enable multiple inputs to be input to a particular bus line thus allowing a system level communication between logic to megacells or megacells to megacells. However, a single tristate can directly couple to only one Line.
The system and method of the present invention provides an innovative bus system of lines which can be programmed to provide data, control and address information to the logic circuits interconnected by the bus system in the context of an electrical/electronics system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits such as megacells to external logic devices and other megacells. Thus, a system can be built using the bus structure of lines by selectively coupling the input signals and output signals from the logic circuits. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.
In one embodiment, a plurality of bussed lines are coupled to the data ports of megacells. A first set of programmable logic is coupled to selective lines of the system of lines and interface logic. The interface logic is coupled to input/output pads of the component for receipt of external input and output of data to be output external to the component. Individual elements of the first set of logic are programmed to selectively couple a particular interface logic element to a particular line and data port to enable the input and output of data to the megacell. It is preferred that, selective lines of the bus system of lines are each coupled to control ports of the megacell and a second set of programmable logic is coupled to the plurality of lines and interface logic elements to selectively couple a particular interface logic element to a particular line and control port to enable the selective input of control data. In another embodiment, the interface logic includes a plurality of programmable three state bi-directional input/out logic, each three state bi-directional input/output logic element coupled to the first set of programmable logic to provide further programmability to selectively couple one of the two external input or output to one of a plurality of the lines of the bus system.
In another embodiment, gateway logic is provided as coupled between the I/O pads and the processing logic. The interface logic can be configured to provide communication enhancements, such as protocols and the like, to enable sophisticated communications to and from the megacells through the bus system thus allowing a flexible scheme of a system on a chip having a bus system.
In other embodiments, programmable connections are provided between the I/O pads and the megacells and between the gateway logic and the megacells.
In addition, the programmable bus structure enables multiple megacells to be coupled together simply by programming the first set of programmable logic, second set of programmable logic and a third set of programmable logic which selectively extends the lines used to convey data, address and control information to additional megacells. This structure therefore enables additional megacells to be coupled without the prior art limitations of hardwiring connections and adding megacells in either the horizontal (width-wise) or vertical (depth-wise) orientation. Furthermore, the system allows the sharing of a common system bus for communicating among megacells.